1) Field of the Invention
This invention relates generally to fabrication of contact or via holes using an Anti-Reflection Coating and chemical-mechanical polishing processes in semiconductor devices and more particularly to the fabrication of an Anti-Reflection Coating composed of Silicon oxynitride (SiON) and chemical-mechanical polish processes used in making contact holes or via holes in ILD or IMD dielectric layers.
2) Description of the Prior Art
Chemical-mechanical polish (CMP) planarization processes are used to level dielectric layers and to polish down metal layer in semiconductor devices. However, these CMP process can create microscratches in dielectric layers that degrade photolithographic performance and create defects. The inventor (s) have found the following problems as described below and in FIGS. 8A to 8D. This is not prior art for the patentability of the invention.
FIG. 8A shows the chemical-mechanical polishing 209 of a dielectric layer 214 overlying a metal line 211 on a substrate 10. FIG. 8B shows the microscratches 216 the inventor has noticed after the chemical-mechanical polish.
Next, an organic bottom anti-reflective coating (BARC) layer 218 and a photoresist layer 224 are formed over the dielectric layer 214 and the microscratches 216. The organic BARC layer 218 and a photoresist layer 224 are exposed to create a photoresist opening 225 (shown as dashed lines).
A problem the inventor has noticed is that the microscratches create reflections that degrade the photoresist pattern.
Next, a via hole is etched in the dielectric layer 214 as shown in FIG. 8C. The photoresist layer is removed.
As shown in FIG. 8C, a barrier layer 228 and metal layer 230 are formed over the dielectric layer and fill the via hole. The barrier layer and metal layer fill in some of the microscratches.
FIG. 8D shows the CMP of the metal layer and barrier layer to form the metal plug 323. However, the microscratches 216 are filled with metal and barrier layer 228. These filled microscratches create defects, short with overlying conductive lines and create photo defects.
Moreover, new microscratches 245 are formed in the dielectric layer by the metal CMP. These new metal chemical-mechanical polish created microscratches 245 cause similar problems.
Therefore, there is a need for a method to prevent microscratches in dielectric layers formed during contact/via hole formation and contact plug/via plug CMP processes.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 5,766,974 (Sardella)--Method of making a dielectric structure for facilitating overetching of metal without damage to inter-level dielectric--that shows an integrated circuit fabrication with a thin layer of oxynitride atop the interlevel dielectric, to provide an etch stop to withstand the overetch of the metal layer. U.S. Pat. No. 5,767,018 (Bell) shows polysilicon etch process using an ARC layer. U.S. Pat. No. 5354712 (Ho)Method for forming interconnect structures for integrated circuits--teaches dielectric layer that is chemical-mechanical polished. U.S. Pat. No. 5,674,784 (Jang et al.) shows a method of forming a polish stop for a CMP process.